1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor integrated device using the same. In particular, the present invention relates to a technology that improves the data retention characteristics of a ferroelectric memory by detecting the degradation of the data retention characteristics and enabling sufficient data to be written so as to eliminate a deficiency in writing data into a memory cell because of such degradation.
2. Description of the Related Art
A nonvolatile, low-power, and high-speed ferroelectric memory has been a focus of attention, particularly since the early 1990s. The ferroelectric memory employs hysteresis characteristics, observed in the polarization-electric field characteristics of a ferroelectric material, as a memory cell.
FIG. 2 shows the hysteresis characteristics observed in the polarization-electric field characteristics (Q-V characteristics). In FIG. 2, the x-axis indicates electric field intensity (the magnitude of voltage), the y-axis indicates polarization (charge), and EC1 and EC2 indicate a coercive field (coercive voltage).
A ferroelectric without polarization (represented by xe2x80x9cAxe2x80x9d in FIG. 2) is polarized (represented by xe2x80x9cBxe2x80x9d) by applying an electric field in the positive direction. The ferroelectric retains its polarization after the electric field has been removed, which is called residual polarization (represented by xe2x80x9cCxe2x80x9d). Next, when the electric field is applied in the negative direction, the ferroelectric is polarized in the opposite direction to the polarization caused by the positive electric field (represented by xe2x80x9cDxe2x80x9d). The ferroelectric retains its polarization after the electric field has been removed (represented by xe2x80x9cExe2x80x9d).
As shown in FIG. 2, the ferroelectric has the polarization even in the absence of an externally applied electric field (voltage). The ferroelectric can be used as a memory cell by taking two different states resulting from the residual polarization as 1 (xe2x80x9cCxe2x80x9d) and 0 (xe2x80x9cExe2x80x9d), respectively. A ferroelectric memory is a device that employs such a ferroelectric as a memory cell capacitor.
Next, as an example of the ferroelectric memory using a ferroelectric material for its memory cells, the configuration and operation of a ferroelectric memory including 2T/2C cells will be described.
FIG. 3A is a circuit diagram showing a cell circuit structure of the ferroelectric memory. FIG. 3B shows waveforms representing the operation of the ferroelectric memory in a cell plate line driving method.
In FIG. 3A, reference numeral 31 is a memory cell, 32 is a sense amplifier, WL is a word line, BL/XBL is a bit line pair for reading/writing data on the memory cell, CP is a cell plate line, and Ns is a ferroelectric memory cell (memory node).
The operation of the ferroelectric memory having the above configuration will be described with reference to FIG. 3B.
First, the word line WL is raised to a logic xe2x80x9cHxe2x80x9d level (t11). Thereafter, the cell plate line CP goes to xe2x80x9cHxe2x80x9d so that the memory cells Ns are selected (t12). When the CP is driven to the xe2x80x9cHxe2x80x9d level, the charge from the memory cells appears on the bit line pair BL/XBL. At this time, the charge is divided by a bit line pair capacitance Cb and a memory cell capacitance (also referred to as a ferroelectric capacitor) Cs, producing electric potential on the bit line pair BL/XBL.
Next, a sense amplifier activating signal SAE goes to xe2x80x9cHxe2x80x9d so that the sense amplifier is activated (t13). Thus, the potential difference of the bit line pair BL/XBL is amplified to VCC and VSS levels, thereby reading data and rewriting xe2x80x9cLxe2x80x9d data.
When the CP is lowered to an xe2x80x9cLxe2x80x9d(VSS) level, xe2x80x9cHxe2x80x9d data is rewritten into the memory cell. Finally, the WL is returned to xe2x80x9cLxe2x80x9d, and thus the operation is completed.
FIG. 4 shows a hysteresis curve of the ferroelectric memory cell during a data read operation.
In FIG. 4, a potential level that appears on the bit line pair BL/XBL is determined by the shape of the hysteresis curve of the ferroelectric memory cell and a bit line pair capacitance Cb. The bit line pair capacitance Cb is represented by the slope of thick lines in FIG. 4. When the cell plate line CP goes to the xe2x80x9cHxe2x80x9d level, VCC potential is applied to the series capacitance of the ferroelectric capacitor and the bit line pair capacitance. Thus, the charge flows out of the ferroelectric capacitor to charge the bit line pair. The reading of data depends on the difference xcex94V between a potential VH in reading xe2x80x9cHxe2x80x9d data and potential VL in reading xe2x80x9cLxe2x80x9d data. Therefore, a larger potential difference xcex94V stabilizes the read operation.
The repetition of polarization reversal causes a ferroelectric to be fatigued and degraded, involving residual polarization loss or the like. The ferroelectric memory performs a destructive read operation. In addition, the fatigue and degradation of the ferroelectric due to polarization reversal occur in both read and write operations. This results in low reliability, such as a reduction in the data retention period and the inability to read and rewrite data.
In the ferroelectric memory, one of the phenomena of fatigue and degradation of a ferroelectric by repetitive read/write operations is called xe2x80x9cimprintxe2x80x9d, where a hysteresis curve is shifted. FIG. 5 shows such an imprint phenomenon.
In FIG. 5, xe2x80x9cIxe2x80x9d is the hysteresis curve of a memory cell before imprint occurs, xe2x80x9cHxe2x80x9d is the hysteresis curve of the memory cell retaining data xe2x80x9c1xe2x80x9d after imprint, and xe2x80x9cLxe2x80x9d is the hysteresis curve of the memory cell retaining data xe2x80x9c0xe2x80x9d after imprint. For example, when data are read from the 2T/2C cell in the case of imprint, the read voltage is reduced to xcex94Vxe2x80x2( less than 0), compared with xcex94V shown in FIG. 4. Thus, the sensitivity margin of the amplified data is decreased significantly, causing faulty operations. As a result, the data retention characteristics of the ferroelectric memory cell become poor.
Moreover, even in the absence of polarization reversal due to write/read operations, the imprint phenomenon occurs by maintaining the spontaneous polarization of a ferroelectric material in the predetermined direction (i.e., the ferroelectric material retains the predetermined data). This reduces residual polarization particularly because the imprint phenomenon causes a deficiency in writing opposite data. Thus, the sensitivity margin of the amplified data is decreased significantly, which leads to the degradation of data retention characteristics, resulting in low reliability.
FIGS. 6A and 6B show a phenomenon of deficiency in writing opposite data, including the coercive field movement (to a higher electric field) in the Q-V characteristics of a ferroelectric in the case of imprint. FIG. 6A shows the imprint phenomenon, where the ferroelectric retains data in the state of point C in FIG. 2. FIG. 6B shows the imprint phenomenon, where the ferroelectric retains data in the state of point E in FIG. 2.
When the imprint phenomenon occurs, the hysteresis curves in FIGS. 6A and 6B, each represented by a broken line, are shifted as indicated by the thick arrows to become the hysteresis curves represented by dotted and thick lines, respectively. The xe2x80x9cshiftxe2x80x9d of the hysteresis curves increases the coercive field EC1 to EC1xe2x80x2 in FIG. 6A and the coercive field EC2 to EC2xe2x80x2 in FIG. 6B. To write sufficient data having the opposite logic to the retained data, it is necessary to apply the electric field (voltage) larger than that before the imprint phenomenon occurs to the ferroelectric capacitors as indicated by the thin arrows in FIGS. 6A and 6B. Also, to provide a sufficient read voltage xcex94V for reading, the electric field (voltage) larger than that before the imprint phenomenon occurs is necessary, just as for writing.
To prevent low reliability caused by imprint, the xe2x80x9cshiftxe2x80x9d of a hysteresis curve resulting from imprint is suppressed, and the occurrence of imprint is detected to correct such xe2x80x9cshiftxe2x80x9d so that the original characteristics are restored, i.e., the imprint compensation is required.
For example, JP 10-69789 A discloses an imprint compensation circuit, whose block diagram is shown in FIG. 15. The operation of the circuit is as follows: after completion of a wafer process, data writing/reading tests are conducted to detect the occurrence of imprint; a high voltage greater than the supply voltage VCC is applied to a write enable (/WE) pad and output enable (/OE) pad from the outside of a chip; the high voltage is applied to both electrodes of a ferroelectric capacitor, thereby compensating for the xe2x80x9cshiftxe2x80x9d of a hysteresis curve and restoring the normal hysteresis loop.
The above method of imprint compensation is effective upon completion of a wafer process. However, it cannot compensate for an imprint phenomenon that may occur under a variety of working conditions after the device actually has been shipped as a product.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a method and circuit that can compensate for the various types of fatigue and degradation, including an imprint phenomenon, even under a variety of working conditions after a ferroelectric memory actually has been shipped as a product.
To achieve the above object, a first semiconductor memory device of the present invention includes a memory cell degradation detector having a first data holding circuit including an element formed of ferroelectric, a memory cell array having a second data holding circuit including an element formed of ferroelectric, and a power supply circuit portion for receiving an output signal from the memory cell degradation detector and supplying an internal supply voltage to the memory cell array. The power supply circuit portion changes a value of the internal supply voltage based on the output signal from the memory cell degradation detector.
According to the first semiconductor memory device, the amount of data (charge) output from a dummy memory cell for reference is detected to estimate the degradation of a ferroelectric memory cell by the most extreme stress in reading/writing data externally at random. When the result of the detection shows that the degradation is considered to have occurred by a certain amount of stress, the potential to be applied to the ferroelectric memory cell during reading/writing, where data are read and written externally at random, is adjusted to be large enough to cause polarization reversal readily. This makes the sufficient writing of data possible and prevents the degradation of data retention characteristics resulting from insufficient polarization reversal because of imprint or poor endurance, so that the reliability of data retention characteristics can be improved. Moreover, since the memory cell degradation detector operates in normal reading/writing, the device can compensate for the various types of fatigue and degradation, including an imprint phenomenon, even under a variety of working conditions after it actually has been shipped as a product.
In the first semiconductor memory device, it is preferable that the internal supply voltage has two or more values, and that the power supply circuit portion switches the values of the internal supply voltage successively based on the output signal from the memory cell degradation detector.
According to this configuration, the potential to be applied to the memory cell can be set precisely in accordance with the degree of degradation of the memory cell characteristics. This can prevent a higher voltage than necessary from being applied to the memory cell and the degradation of characteristics, caused by the high-voltage application to the memory cell, from being accelerated. Thus, the side effect of an increased voltage in writing data can be suppressed.
In the first semiconductor memory device, it is preferable that the value of the internal supply voltage is lower than that of an external supply voltage.
According to this configuration, the voltage to be applied to the memory cell can remain a low voltage. Therefore, the acceleration of degradation by the high-voltage application can be suppressed, and also current can be supplied sufficiently as well as responsively to the circuit that consumes a large amount of current, such as a cell plate or sense amplifier. Thus, this can provide improved reliability and high speed, compared with supplying a stepped-up potential from an external power supply VDD.
In the first semiconductor memory device, it is preferable that the first data holding circuit is provided with a plurality of data holding circuits, each of which includes a data holding element pair formed of ferroelectric and a data read line pair connected to each of the data holding element pair and has a different capacitance ratio of the data holding element pair to the data read line pair.
In the first semiconductor memory device, it is preferable that each of the data holding circuits has a different capacitance value of the data holding element pair or different capacitance value of the data read line pair.
In the first semiconductor memory device, it is preferable that the first data holding circuit includes a first data holding element pair formed of ferroelectric, a first data read line pair connected to each of the first data holding element pair, and a first data amplifier for receiving a signal through the first data read line pair; the second data holding circuit includes a second data holding element pair formed of ferroelectric, a second data read line pair connected to each of the second data holding element pair, and a second data amplifier for receiving a signal through the second data read line pair; the capacitance ratio of one element of the first data holing element pair to one line of the first data read line pair is the same as that of one element of the second data holding element pair to one line of the second data read line pair, and the capacitance ratio of the other element of the first data holding element pair to the other line of the first data read line pair is different from that of the other element of the second data holding element pair to the other line of the second data read line pair.
In this case, it is preferable that a capacitance value of one line of the first data read line pair is the same as that of one line of the second data read line pair, and that a capacitance value of the other line of the first data read line pair is smaller than that of the other line of the second data read line pair.
According to the above configuration, the degree of degradation progress of the memory cell characteristics can be detected successively by comparing data from the memory cell with an expected value, using the memory cell degradation detector. The memory cell degradation detector may include a plurality of data holding circuits, each having a different capacitance ratio (Cb/Cs) of a dummy bit line pair to a dummy memory cell; such a difference in capacitance ratio can be achieved, e.g., by providing the dummy bit line pairs with different wiring length or the dummy memory cells with different structure, based on the Q-V characteristics of the ferroelectric when imprint degradation is caused. Alternately, the memory cell degradation detector may include the data holding circuits, where one bit line of the dummy bit line pair has the same capacitance value and Cb/Cs as those of each line of the bit line pair in the memory cell array, and the other has a capacitance value and Cb/Cs different from those of each line of the bit line pair in the memory cell array, e.g., the Cb/Cs value of the other dummy bit line smaller than that in the memory cell array.
The application of potential that corresponds to the degree of degradation of the memory cell characteristics allows polarization reversal to be caused readily. This makes the sufficient writing of data possible and prevents the degradation of data retention characteristics resulting from insufficient polarization reversal because of imprint or poor endurance. Thus, the reliability of data retention characteristics can be improved. Moreover, this can prevent the imprint phenomenon in the dummy memory cell due to repetitive reading/writing from being restored.
In the first semiconductor memory device, it is preferable that the first data holding circuit includes a plurality of first data holding elements formed of ferroelectric and a plurality of data read lines connected to the first data holding elements, and that the reading/writing of data with respect to the first data holding elements are performed only when the power is turned on.
This configuration provides reference cells on which the reading/writing of data are performed only when the power is turned on. Therefore, the degradation of the memory cell by stress applied thereto when the power is on/off can be recreated and detected. Thus, the imprint degradation, including the degradation of data retention characteristics that occurs during the power-off period, can be detected.
In the first semiconductor memory device, it is preferable that the first data holding circuit includes a plurality of first data holding elements formed of ferroelectric and a plurality of data read lines connected to the first data holding elements, and that the reading/writing of data with respect to the first data holding elements are performed when the power is turned on and when data are read from and written into the memory sell array.
This configuration provides reference cells on which the reading/writing of data are performed when the power is turned on and each time data are read from and written into the ferroelectric memory cell, where data are read and written externally at random. Therefore, the degradation of the memory cell by the stress of poor characteristics resulting from repetitive polarization reversal and of data loss during the power-off period can be recreated and detected. Thus, the imprint degradation, including the degradation of data retention characteristics that occurs during the power-off period and the degradation by writing data into the memory cell, can be detected.
In the first semiconductor memory device, it is preferable that the first data holding circuit includes a first data holding element formed of ferroelectric, a first data read line connected to the first data holding element, a third data holding element formed of ferroelectric, and a third data read line connected to the third data holding element, and that the reading/writing of data with respect to the first data holding element are performed only when the power is turned on, while the reading/writing of data with respect to the third data holding element are performed when the power is turned on and each time data are read from and written into the memory cell array.
This configuration provides dummy memory cells for individual reference: the dummy memory cell on which the reading/writing of data are performed only when the power is turned on; the dummy memory cell on which the reading/writing of data are performed when the power is turned on and each time data are read from and written into the ferroelectric memory cell, where data are read and written externally at random. Therefore, the degradation of the memory cell by stress applied thereto when the power is on/off and the degradation by the stress of poor characteristics resulting from a write operation and of data loss during the power-off period can be recreated and detected in a chip. Thus, the imprint degradation by residual polarization during the power-off period and by reading/writing of data on the memory cell involving polarization reversal can be detected.
In the first semiconductor memory device, it is preferable that the first data holding circuit includes a first data holding element formed of ferroelectric, a first data read line connected to the first data holding element, a third data holding element formed of ferroelectric, and a third data read line connected to the third data holding element; the reading/writing of data with respect to the first data holding element are performed only when the power is turned on, while the reading/writing of data with respect to the third data holding element are performed when the power is turned on and each time data are read from and written into the memory cell array, and after the reading/writing of data with respect to the first and third data holding elements in turning the power on, a refresh operation is performed for the memory cell array.
According to this configuration, the imprint phenomenon that has occurred during the power-off period can be restored in such a manner that the refresh operation is performed for the memory cell array after completion of read/write operations on the reference cells when the power is turned on. Moreover, the data stored in the memory cell of the memory cell array, which have not been accessed during the time the power is on, are accessed at least once during the power-on period. Thus, the history of stress applied to the reference cells, where data are read and written only when the power is turned on, can correspond to the history of stress applied to the memory cells that are not accessed externally during the power-on period.
In the first semiconductor memory device, it is preferable that the data to be written into the first and third data holding elements are constant regardless of data input externally to the memory cell array.
According to this configuration, the data having a fixed value are written into the reference cells, e.g., an internal supply voltage VINT1 is written into one line of the bit line pair and VSS is written into the other line, allowing the reference cells to cause imprint readily. Therefore, the degradation of the memory cell array by stress, where data are read and written externally at random, can be recreated and detected. Moreover, only VSS is written into both of the complementary bit lines, which can prevent the imprint phenomenon in the dummy memory cell from being restored.
In the first semiconductor memory device, it is preferable that the power supply circuit portion includes an input circuit for recognizing a voltage level of an external signal, a first means for outputting the internal supply voltage to the outside of a chip, and a second means for transmitting the internal supply voltage to the first means based on an output signal from the input circuit, and that a value of the internal supply voltage is changed in accordance with the voltage level of the external signal.
This configuration provides a test circuit, whose operation mode can be set externally, in the power supply circuit portion. Therefore, the correlation between the degree of degradation progress and the power supply voltage level can be taken before applying stress in advance. Thus, the potential within a chip that is changed according to the degree of degradation progress is confirmed even after assembly by sealing, so that the degree of degradation can be confirmed by this potential. Moreover, since the level of the internal supply voltage can be set arbitrarily from the outside of a chip, any voltage stress can be applied externally to the memory cell array. Thus, the resistance of the ferroelectric memory cell itself to stress can be evaluated. In addition, the testing and screening of a device (chip) with poor characteristics in terms of reliability can be conducted in the following manner: the output of the data holding circuit or the power supply voltage level are monitored during testing so as to detect the degree of fatigue and degradation of the ferroelectric memory cell.
To achieve the above object, a second semiconductor memory device of the present invention includes: a memory cell array having a plurality of data holding elements formed of ferroelectric and a plurality of data read lines connected to the data holding elements; a first data amplifier connected to the data lead lines, for outputting data of the data holding elements to the outside; a first power supply circuit; a second data amplifier for receiving an output signal from the first power supply circuit and signals through the data read lines, and a second power supply circuit for receiving an output signal from the second data amplifier and supplying an internal supply voltage to the memory cell array. The second power supply circuit changes a value of the internal supply voltage based on the output signal from the second data amplifier.
The second semiconductor memory device provides a sense amplifier for reading data in addition to a sense amplifier for transmitting data. Therefore, the degradation of the memory cell itself by stress can be detected, the memory cell being selected randomly for reading/writing data externally. When it is assumed that the occurrence of degradation by a certain amount of stress makes it difficult to cause polarization, the potential to be applied to the memory cell in rewriting data and writing externally input data is adjusted to be large enough to cause polarization reversal satisfactorily, and thus data can be written. Consequently, the characteristics in terms of reliability can be improved.
To achieve the above object, a semiconductor integrated device of the present invention includes a plurality of the first or the second semiconductor memory devices. The semiconductor integrated device further includes a selecting circuit, to which data signals from the semiconductor memory devices are coupled, for selecting any one of the semiconductor memory devices and a control circuit for controlling the selecting circuit so that an unselected semiconductor memory device is selected based on the data signal from the semiconductor memory device selected by the selecting circuit.
This semiconductor integrated device includes a plurality of ferroelectric memories that can output signals for detecting degradation to the outside and a ferroelectric memory controller that selects and operates the ferroelectric memory to be used. Therefore, the semiconductor integrated device can detect the ferroelectric memory whose characteristics have been degraded under a variety of working conditions, stop that ferroelectric memory operating, and employ unused ferroelectric memory instead.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.